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| M62230FP LCD Matrix Regulator REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Description The M62230FP is a semiconductor circuit for LCD matrix regulator, which will generate the divided-voltage to drive LCD matrix. By changing the connection of R pin (i.e., Change the internal resistor ratio), M62230FP can support divided voltage ratio ranging from 1/5 bias to 1/13 bias. The high stability and any desired voltage levels is possible, since the variable voltage regulator for VREF is built-in. Features * Adjustable type voltage divider. (The setting range of internal resistor is from 1/5 bias to 1/13 bias) * 5 resident buffer-Amp. (5 divided output) * Low power dissipation. (1.8 mA Typ.) * Resident voltage-variable regulator for VREF. Application To drive LCD. Recommend Operating Conditions (Ta = 25C) Supply voltage range: GND - VCC: (if V1 > -1 V, it is necessary to support VIN).... -30 to -10 V (To set VCC, VREF, in order that both |0 - V2| & |VCC - V5| are larger than 1 V) Recommend input voltage GND - VREF: VREF VCC.............................................. -30 to -6 V Block Diagram REGOUT 7 REGIN 8 - + -1.38 V VIN3 9 VIN2 10 GND 12 R VIN 11 13 VO1 14 VO2 15 VO3 16 VO4 17 VO5 R R R R 20 VREF 19 VIN5 18 VCC 4R R 1 R6 R R R R 2 R5 R1 6 R2 5 R3 4 R4 3 REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Page 1 of 6 M62230FP Pin Arrangement M62230FP R6 R5 R4 R3 R2 R1 REGOUT REGIN VIN3 1 2 3 4 5 6 7 8 9 20 VREF 19 VIN5 18 VCC 17 VO5 16 VO4 15 VO3 14 VO2 13 VO1 12 GND 11 VIN (Top view) Outline: PRSP0020DA-A (20P2N-A) VIN2 10 REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Page 2 of 6 M62230FP Explanation of Terminals Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 R6 R5 R4 R3 R2 R1 REGOUT REGIN VIN3 VIN2 VIN GND VO1 VO2 VO3 VO4 VO5 VCC VIN5 VREF VCC power (-Power) VIN5 input Reference voltage input pin Symbol Function If the voltage of each pin can satisfy the following condition: VO6 VO5 VO4 VO3 VO2 VO1 These pins will be used. Please refer to page 5 to set the bias ratio. Regulator output for VREF to use The inverting input pin of REG OP-Amp VIN3 input VIN2 input VIN Power GND Pin Divided-voltage output pin To set VCC & VREF, in order that 0 - V2 1 V To set VCC & VREF, in order that V5 - VCC 1 V if V1 > -1.0 V, it is necessary to support VIN if V1 < -1.0 V, this pin connect to GND REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Page 3 of 6 M62230FP Absolute Maximum Ratings (Ta = 25C, unless otherwise noted) Item Supply voltage Maximum output current Power dissipation Thermal derating Operating temperature Storage temperature Symbol VCC IOUT Pd K Topr Tstg Ratings -36 to 0 30 550 5.5 -20 to +75 -40 to +125 Unit V mA mW mW/C C C Conditions Ta = 25C Ta > 25C Electrical Characteristics (VCC = -16 V, VIN = GND, VREF = -12 V, Resistor setting = 5R, Ta = 25C, unless otherwise noted) Limits Item Supply voltage Dissipation current Output voltage ratio 1 Output voltage ratio 2 Output voltage ratio 3 Output voltage ratio 4 Output voltage ratio 5 Output voltage ratio 6 Resistor ratio 1 Resistor ratio 2 Resistor ratio 3 Resistor ratio 4 Resistor ratio 5 Resistor ratio 6 Resistance Load regulation of output voltage 1 Load regulation of output voltage 2-1 Load regulation of output voltage 3-1 Load regulation of output voltage 2-2 Load regulation of output voltage 3-2 Load regulation of output voltage 4 Load regulation of output voltage 5 Output voltage of regulator Load regulation of VREF Symbol VCC ICC RVO1 RVO2 RVO3 RVO4 RVO5 RVO6 RR1 RR2 RR3 RR4 RR5 RR6 R V1 V2-1 V3-1 V2-2 V3-2 V4 V5 VREG REG-L Min. -35 1.98 1.98 8.90 4.45 4.45 8.90 -1.45 Typ. 1.80 2.00 2.00 9.00 4.50 4.50 9.00 4 5 6 7 8 9 20 -1.38 Max. -10 2.02 2.02 9.10 4.55 4.55 9.10 20 20 20 20 20 20 20 -1.31 50 Unit V mA k mV mV mV mV mV mV mV V mV VREF = -16 V V2 / V1 (V5 - V3) / (V5 - V4) V5 / V1 V5 / V2 V5 / (V5 - V3) V5 / (V5 - V4) Resistor between VIN3 and R1 / resistor between R1 and R2 Resistor between VIN3 and R2 / resistor between R1 and R2 Resistor between VIN3 and R3 / resistor between R1 and R2 Resistor between VIN3 and R4 / resistor between R1 and R2 Resistor between VIN3 and R5 / resistor between R1 and R2 Resistor between VIN3 and R6 / resistor between R1 and R2 Resistor between R1 and R2 +200 A < IOUT1 < +10 mA +200 A < IOUT2 < +10 mA +200 A < IOUT3 < +10 mA -10 mA < IOUT2 < -200 A -10 mA < IOUT3 < -200 A -20 mA < IOUT4 < -200 A -20 mA < IOUT5 < -200 A Buffer output -10 mA < IREG < +2 mA Test Conditions REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Page 4 of 6 M62230FP The Setting Method of Divided-voltage R + - VO1 R + - VO2 Rx + - VO3 R + - VO4 R + - VO5 R VREF Rx R 2R 3R 4R 5R 6R 7R 8R 9R 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12 1/13 Bias Ratio Example of Setting 9 pin-6 pin short, 10 pin-5 pin short 9 pin-6 pin short, 10 pin-4 pin short 9 pin-6 pin short, 10 pin-3 pin short 10 pin-6 pin short 10 pin-5 pin short 10 pin-4 pin short 10 pin-3 pin short 10 pin-2 pin short 10 pin-1 pin short REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Page 5 of 6 M62230FP Package Dimensions JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A MASS[Typ.] 0.3g 20 11 HE *1 E F 1 Index mark 10 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. c *2 D A2 A1 Reference Symbol Dimension in Millimeters *3 e bp y Detail F D E A2 A1 A bp c HE e y L Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 A REJ03D0855-0201 Rev.2.01 Nov 14, 2007 Page 6 of 6 L Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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